#define ENABLE_BIT_DEFINITIONS #include #include void transmit(unsigned char data) { while (!(UCSR0A & (1 << UDRE0))); UDR0 = data; } long delay(unsigned char tm) { long n = 0; for (unsigned char m = 0; m < tm; m++) { while (n < 150) n++; n = 0; } return n; } #define MAX_PSZ 938 #define MIN_PSZ 520 char vals[MAX_PSZ]; unsigned short packetSize = MIN_PSZ;//796;//521;//796; unsigned short pos; unsigned char del = 0; unsigned char syncMode = 0; unsigned char syncChnl = 0; unsigned char syncVal1 = 16;// + 110; unsigned char syncVal2 = 32;// + 100; unsigned char adcsra = 0xd7; unsigned char syncOk = 0xfe; unsigned char chMode = 2; unsigned long nn; #define SYNC_TIMEOUT_DEF (40000 / 10) unsigned short SYNC_TIMEOUT = SYNC_TIMEOUT_DEF; void do_sync_pos() { ADMUX = 0x20 | syncChnl; SYNC_TIMEOUT = SYNC_TIMEOUT_DEF * (adcsra & 0x7); nn = 0; do { ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); nn++; } while ((ADCH > syncVal1) && (nn < SYNC_TIMEOUT)); if (nn == SYNC_TIMEOUT) return; nn = 0; do { ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); nn++; } while ((ADCH < syncVal2) && (nn < SYNC_TIMEOUT)); if (nn == SYNC_TIMEOUT) return; syncOk = 0xfd; } void do_sync_neg() { ADMUX = 0x20 | syncChnl; SYNC_TIMEOUT = SYNC_TIMEOUT_DEF * (adcsra & 0x7); nn = 0; do { ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); nn++; } while ((ADCH < syncVal2) && (nn < SYNC_TIMEOUT)); if (nn == SYNC_TIMEOUT) return; nn = 0; do { ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); nn++; } while ((ADCH > syncVal1) && (nn < SYNC_TIMEOUT)); if (nn == SYNC_TIMEOUT) return; syncOk = 0xfd; } void transmit_magic() { // transmit MAGIC transmit(0x10); transmit(0x10); transmit(syncOk); transmit(0x10); transmit((unsigned char)(packetSize / 4)); } void packet_ch1() { ADMUX = 0x20; // capture data from ADC to memory here for (pos = 0; pos < packetSize; pos++) { ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos] = ADCH; } // transmit MAGIC transmit_magic(); // transmit a rest of captured packet for (pos = 0; pos < packetSize; pos++) { transmit(vals[pos]); } } void packet_ch2() { // capture data from ADC to memory here for (pos = 0; pos < packetSize; ) { ADMUX = 0x20; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; ADMUX = 0x21; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; } // transmit MAGIC transmit_magic(); // transmit a rest of captured packet for (pos = 0; pos < packetSize; pos++) { transmit(vals[pos]); } } void packet_ch4() { // capture data from ADC to memory here for (pos = 0; pos < packetSize; ) { ADMUX = 0x20; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; ADMUX = 0x21; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; ADMUX = 0x22; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; ADMUX = 0x23; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[pos++] = ADCH; } // transmit MAGIC transmit_magic(); // transmit a rest of captured packet for (pos = 0; pos < packetSize; pos++) { transmit(vals[pos]); } } void packet_del() { // transmit MAGIC transmit_magic(); // capture data from ADC and transmit for (pos = 0; pos < packetSize; ) { for (char c = 0; c < chMode; c++) { ADMUX = 0x20 + c; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); vals[c] = ADCH; pos++; } for (char c = 0; c < chMode; c++) { transmit(vals[c]); } delay(del); } } void single_del() { transmit(0x10); transmit(0x10); transmit(syncOk); transmit(0x10); transmit(4); for (char c = 0; c < 4; c++) { if (c >= chMode) { transmit(128); continue; } ADMUX = 0x20 + c; ADCSRA = adcsra; while ((ADCSRA & 0x10) == 0); transmit(ADCH); } delay(63); for (unsigned char s = 0; s < ((del - 4) * 4); s++) delay(63); } #define SYNC_OFF 0 #define SYNC_POS 1 #define SYNC_NEG 2 #define CMD_ACDC 0x04 #define CMD_BUFSZ 0x08 #define CMD_XSET 0x10 #define CMD_YSET 0x11 #define CMD_CHMODE 0x12 #define CMD_SYNCMODE 0x20 #define CMD_SYNC_VAL1 0x21 #define CMD_SYNC_VAL2 0x22 unsigned char cmd1 = 0, cmd2 = 0, cmd3 = 0, cmd4 = 0; int main(void) { // Ports dir DDRC = 0x00; PORTC = 0x00; DDRB = 0x07; DDRB = 0x07; PORTB = 0x01 << 1; DDRD = 0x00; // init UART UBRR0 = 8;//3; 8=8MHz RC UBRR0 = 21; // 21=20MHz 16=16MHz Quartz 115200baud UCSR0A |= 0x2; // U2Xn = 1 UCSR0B = ((1 << RXEN0) | (1 << TXEN0) | (1 << RXCIE0)); UCSR0C = (3< 0 && cmd4 < 8) { adcsra = 0xd0 | (cmd4 & 0x07); del = 0; } if (cmd4 > 7 && cmd4 < 16) { adcsra = 0xd7; // slowest del = (cmd4 & 0x07) + 1; } } else if (cmd3 == CMD_YSET) { PORTB = (cmd4 & 0x03) << 1; } else if (cmd3 == CMD_SYNCMODE) { syncMode = cmd4 & 0x03; syncChnl = (cmd4 >> 2) & 0x03; } else if (cmd3 == CMD_SYNC_VAL1) { syncVal1 = cmd4; } else if (cmd3 == CMD_SYNC_VAL2) { syncVal2 = cmd4; } else if (cmd3 == CMD_CHMODE) { chMode = cmd4 & 0x07; if (chMode > 4) chMode = 1; if (chMode == 0) packetSize = MIN_PSZ; else packetSize = MAX_PSZ; } }